Integrated circuits include a large number of transistors formed on a semiconductor substrate, such as silicon. The transistors may be a variety of types such as NMOS and PMOS transistors. Examples of integrated circuits of this type are memory devices such as static random access memories ("SRAMs") and dynamic random access memories ("DRAMs"). Further, there are several varieties of DRAMs such as synchronous DRAMs ("SDRAMs") and packetized DRAMs.
It is common in integrated circuits, particular integrated circuit memory devices, for the substrate of the integrated circuit to be biased at ground potential. However, it is also common for the substrate to be biased to a negative voltage. Biasing the substrate of the integrated circuit at a negative voltage lowers the sensitivity of threshold voltages to a phenomenon known as the "body effect," increases punch-through voltages, lowers the diffusion-to-substrate capacitance and provide other advantages. For example, a negative substrate voltage lowers subthreshold leakage on clocked depletion transistors and protects the chip against forward biasing of the substrate due to voltage undershoots at the inputs of the integrated circuit. The negative voltage is typically provided by a negative bias voltage generator, such as a charge pump. A wide variety of conventional charge pumps may be used for this purpose, one of which is illustrated in FIG. 1 to bias the substrate of an integrated circuit memory device 10. The memory device 10 includes conventional memory circuits 12 that are formed by a large number of transistors fabricated on the substrate of the memory device 10. The memory circuits 12 are coupled to external devices through a bus system 14 such as an address bus, a data bus, and a control/status bus.
Also fabricated on the substrate of the integrated circuit memory device 10 is a negative voltage generator 20 having an output voltage line 26 and a control voltage input line 28. The output voltage line 26 is coupled to the substrate of the memory device 10 to apply a substrate bias voltage Vbb to the substrate. The input control line 28 is also coupled to the substrate to apply the substrate voltage Vbb to a control input of the negative voltage generator 20. In operation, the magnitude of the voltage generated by the negative voltage generator 20 is controlled by the input control voltage on line 28 to regulate the bias voltage Vbb to a predetermined value. When the bias voltage Vbb tends to decrease for various reasons, such as an increase in load, the reduced bias voltage Vbb coupled to the input control line 28 causes the negative voltage generator 20 to bring the bias voltage Vbb back to the predetermined voltage. Negative voltage generators 20 having the characteristics described above are conventional and are described in, for example, U.S. Pat. No. 5,574,691 which is incorporated herein by reference.
Commercially available integrated circuits, such as memory devices, are typically tested throughout and after their manufacturing process. Generally, these integrated circuits are initially tested while they are still in wafer form before being separated to individual integrated circuit dies. Final testing of the integrated circuit occurs after the integrated circuit die has been placed in a package having externally accessible contacts. In the testing of integrated circuits, it is generally desirable to test under conditions in which the integrated circuit is more likely to fail compared to normal operating conditions. For example, for integrated circuits having a grounded substrate, it is desirable to test the integrated circuit with the substrate at a negative voltage. For integrated circuits having a substrate that is biased to a negative voltage during normal operation, it is desirable to test the integrated circuit with the substrate at a voltage that is more negative than the normal substrate bias voltage. If the integrated circuit operates properly at this test voltage, then it is more likely to work properly at the voltage to which the substrate is biased during normal operating conditions.
A variety of techniques have been used to provide a substrate voltage for test purposes. For example, as illustrated in FIG. 2, an integrated circuit, such as a memory device 30 having memory circuits 12, includes an enable circuit 32 having an externally accessible input terminal 34. The memory device 30 also includes a negative voltage generator 36 having an enable input terminal 38 connected to an output terminal 40 of the enable circuit 32. The negative voltage generator 36 has an output terminal 42 coupled to the substrate of the memory device 30. When enabled, the negative voltage generator 36 outputs a negative test voltage V.sub.TEST that is more negative than the substrate voltage Vbb produced by a different negative voltage generator (not shown in FIG. 2).
In operation, one or more signals are applied through one or more input lines 34 to the enable circuit 32, thereby causing the enable circuit 32 to generate an enable signal. The enable signal is applied to the enable input terminal of the negative voltage generator 36 which then generates the test voltage V.sub.TEST. Since the test voltage V.sub.TEST is more negative than the normal bias voltage Vbb, some tests performed on the memory circuits 12 in this condition may be more likely to fail as compared to normal operation. Thus, testing using the enable circuit 32 and negative voltage generator 36 of FIG. 2 is more likely to discover faults in the memory circuits 12 during testing.
Although the approach shown in FIG. 2 can successfully bias the substrate of the integrated circuit 30 to a negative test voltage that is more negative than the normal substrate voltage Vbb, it requires the inclusion of a negative voltage generator 36 for integrated circuits having a normally grounded substrate or a second negative voltage generator 36 for integrated circuits having a normally negatively biased substrate. The need to fabricate a negative voltage generator 36 or an additional negative voltage generator 36 in the memory device 30 increases the cost of the memory device 30 or other integrated circuit and can consume a significant quantity of surface area. Increasing the cost, complexity, and size of a memory device 30 solely for the purpose of facilitating factory testing is considered undesirable since this additional circuitry is used only briefly during the life of the integrated circuit. Furthermore, although the negative voltage generator 36 can generate a suitable test voltage V.sub.TEST, the magnitude of the test voltage V.sub.TEST cannot be varied. However, it is often desirable to vary the test voltage to alter the severity of the test depending on a variety of factors.
One technique for applying a negative test voltage to a substrate in integrated circuits having an existing negative voltage generator is described in U.S. Pat. No. 5,619,459 to Gilliam. The Gilliam patent teaches continuously activating a negative voltage substrate pump during testing, and then regulating the substrate voltage to a predetermined value using a voltage sensitive shunt. However, this shunt regulator approach may use excessive current for many applications. Furthermore, a significant amount of circuitry is required to implement the shunt regulator and the control circuitry for the regulator and charge pump.
The above-described disadvantages of the approaches described above can be eliminated by simply coupling a test voltage to the substrate of an integrated circuit the integrated circuit from an external source, as illustrated in FIG. 3. As shown in FIG. 3, an integrated circuit, such as a memory device 52 containing memory circuits 12, has a pair of externally accessible input terminals 54, 56. The input terminal 56 controls the conductive state of a pass gate 58 which selectively couples the input terminal 54 to the substrate.
In operation, a negative test voltage is applied to the input terminal 54 which is then selectively coupled to the substrate by the pass gate 58. The technique shown in FIG. 3 avoids the disadvantages of FIG. 2 since the magnitude of the test voltage V.sub.TEST can be varied at will and only a negligible amount of additional circuitry is required, i.e., the circuitry in the pass gate 58. However, the technique shown in FIG. 3 has the disadvantage of allowing the substrate to be inadvertently coupled to an external pin which may be at a voltage that can damage the integrated circuit 52. Furthermore, it is often not possible to couple a large negative voltage from an external terminal to the substrate without forward biasing semiconductor junctions that are also coupled to the input terminal 54.
There is therefore a need for a technique to apply to the substrate a negative test voltage that has an externally adjustable magnitude without requiring the addition of significant circuitry or risking the forward biasing of semiconductor junctions.